Richard Norman, Olivier Valorge, Yves Blaquière, Etienne Lepercq, Yan Basile-Bellavance, Youssef El-Alaoui, Richard Prytula, Yvon Savaria, « An Active Reconfigurable Circuit Board,» 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference , June, pp. 351-354, 2008. Richard Norman, Etienne Lepercq, Yves Blaquière, Olivier Valorge, Yan Basile-Bellavance, Richard Prytula and Yvon Savaria, « An Interconnection Network for a Novel Reconfigurable Circuit Board,» 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference , June, pp. 129-132, 2008. Olivier Valorge, Anh Tuan Nguyen, Yves Blaquière, Richard Norman and Yvon Savaria, « Digital Signal Propagation on a Wafer-Scale Smart Active Programmable Interconnect,» IEEE International Conference on Electronics, Circuits and Systems (ICECS'08), August-September, 2008. Yan Basile-Bellavance, Etienne Lepercq, Yves Blaquière and Yvon Savaria, « Hardware/Software System Co-Verification of an Active Reconfigurable Board with SystemC-VHDL,» IEEE International Conference on Electronics, Circuits and Systems (ICECS'08) , August-September, 2008. Mohammed Bougataya, Ahmed Lakhsasi, Richard Norman, Richard Prytula, Yves Blaquière and Yvon Savaria, « Steady State Thermal Analysis of a Reconfigurable Wafer-scale Circuit Board,» Canadian Conference on Electrical and Computer Engineering (CCECE), May, pp. 411-416, 2008. Yves Blaquière, Yvon Savaria and J. El Fouladi, « Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os,» IEEE International conference on Electronics, Circuits and Systems (ICECS'07), December, 2007. Marc-André Cantin, Yves Blaquière, Éric Granger, Yvon Savaria, et Pierre Lavoie, « Implementation of the Fuzzy ART Neural Network for Fast Clustering of Radar Pulses,» Proceedings of the IEEE International Symposium on Circuit and Systems , accepté pour publication, 1998. E. Granger, Y. Blaquière, Y. Savaria, M.-A. Cantin, and P. Lavoie, « A VLSI Architecture for Fast Clustering with Fuzzy ART Neural Networks,» Journal of Microelectronics System Integration, vol. 5, no. 1, pp. 3-17, mars, 1997. Yves Blaquière, Michel R. Dagenais, et Yvon Savaria. « Timing Analysis Speed-up Using a Hierarchical and a Multimode Approach, » IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 244-255, février 1996. Éric Granger, Yves Blaquière, Yvon Savaria, Marc-André Cantin, et Pierre LAVOIE. « A VLSI Architecture for Fast Clustering with Fuzzy ART Neural Networks, » Proceedings of the 1996 International Workshop on Neural Networks for Identification, Control, Robotics, and Signal/Image Processing (NICROSP'96 Workshop), pp. 117-125, août 1996. Yves Blaquière, Gabriel Gagné, Yvon Savaria, et Claude Évéquoz. « A New Efficient Algorithmic-Based SEU Tolerant System Architecture, » 32nd Annual International Nuclear and Space Radiation Effects Conférence, août 1995. Yves Blaquière, Gabriel Gagné, Yvon Savaria, et Claude Évéquoz. « A New Efficient Algorithmic-Based SEU Tolerant System Architecture, » IEEE Transaction on Nuclear Science, 1599-1606, décembre 1995. Yves Blaquière, Gabriel Gagné, Yvon Savaria, et Claude Évéquoz. « Cost Analysis of a New Algorithmic-Based Soft-Error Tolerant Architecture, » IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 189-197, novembre 1995. Yves Blaquière, Michel R. Dagenais, et Yvon Savaria. « A New Accurate and Hierarchical Timing Analysis Approach, » dans Proceedings of the IEEE European Design Automation Conference, 449-454, 1993. Yves Blaquière. « Évaluation rapide des performances temporelles des circuit VLSI: une approche dynamique et hiérarchique, » Thèse de doctorat, École Polytechnique de Montréal, août 1992. Yves Blaquière, Michel R. Dagenais, et Yvon Savaria. « Timing Analysis of VLSI Circuits: A Dynamic and Hierarchical Approach, » dans Proceedings of the IEEE International Symposium on Circuit and Systems, 2399-2402, juin 1991. Yves Blaquière et Jacob Davidson. « VHDL Design of a Priority Interrupt Controler and Synchronizer for MC68008 Microprocessor, » dans Microprocessor and MicroSystem. Butterworth Scientific Limited, octobre 1990. Yves Blaquière et Yvon Savaria. « Area Overhead Analysis of SEF: a Design Methodology for Tolerating SEU, » 1987 Annual Conference on Nuclear and Space Radiation Effects, juilllet 1987. Yves Blaquière et Yvon Savaria. « Area Overhead Analysis of SEF: a Design Methodology for Tolerating SEU, » IEEE Transactions on Nuclear Science, 1481-1486, décembre 1987. Yves Blaquière. « Analyse détaillée du coût en matériel apporté par l'approche SEF, » Mémoire de maîtrise, École Polytechnique de Montréal, août 1986. Yves Blaquière et Yvon Savaria. « Area Overhead Analysis of Soft-Errors Filtering register,» Conférence canadienne sur le VLSI, 26-29, novembre 1985. Yves Blaquière Octobre, 2008
