Publications de Yves Blaquière
last updated February 2015
- Darvishi M*, Audet Y, Blaquière Y, Thibeault C, Pichette S, Tazi FZ, « Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation,» IEEE Transactions on Nuclear Science, vol. 61, no. 6, pp. 3535-3542, 2015.
- Laflamme-Mayer N*, Blaquière Y, Savaria Y, Sawan M, « A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems,» IEEE Transactions on Circuits and Systems I, 2014.
- Blaquière Y, Berrima S*, Basile-Bellavance Y*, Savaria Y, « Design and Validation of a Novel Reconfigurable and Defect Tolerant JTAG Scan Chain,» IEEE International Symposium on Circuits and Systems, ISCAS, 2014.
- Darvishi M*, Audet Y, Blaquière Y, Thibeault C, « Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation,» IEEE Nuclear and Space Radiation Effects Conference, July 14-18, Paris, France, 2014, Available: .
- Souari A*, Thibeault C, Blaquière Y, Velazco R, « Towards a Realistic SEU Effects Emulation on SRAM Based FPGAs,» IEEE Nuclear and Space Radiation Effects Conference, Paris, France, 2014.
- Diop MD*, Radji M*, Hamoui AA, Blaquière Y, Izquierdo, R., « Evaluation of Anisotropic Conductive Films Based on Vertical Fibers for Post-CMOS Wafer-Level Packaging,» IEEE Transactions on Components, Packaging and Manufacturing Technology, (2013 Best Paper Award), 2013.
- Laflamme-Mayer N*, Sawan M, Blaquière Y, « A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems,» 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings, 2013.
- Laflamme-Mayer N*, Andre W*, Valorge O*, Blaquière Y, Sawan M, « Configurable input-output power pad for wafer-scale microelectronic systems,» IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013.
- Baratli K*, Lakhssassi A, Blaquière Y, Savaria Y, « A netlist pruning tool for an electronic system prototyping platform,» IEEE 11th International New Circuits and Systems Conference, NEWCAS,, 2013.
- Hussain W*, Savaria Y, Blaquière Y, « An interface for the I2C protocol in the WaferBoard,» IEEE International Symposium on Circuits and Systems, ISCAS, 2013.
- Guillemot M*, Blaquière Y, Savaria Y, « Software Rendering Methods to Display Software Wafer Scale Integrated Circuit Dataset,» IEEE Canadian Conference on Electrical and Computer Engineering, CCECE, 2013.
- Nguyen HH, Guillemot M.*, Savaria Y, Blaquière Y, « A new approach for pin detection for an electronic system prototyping reconfigurable platform,» Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP, 2012.
- Saydé M*, Lakhssassi A, Bougataya M*, Terkawi O, Blaquière Y, « SoC systems thermal monitoring using embedded sensor cells unit,» IEEE Midwest Symposium on Circuits and Systems, 2012.
- Al-Terkawi Hasib O, Andre W*, Blaquière Y, Savaria Y, « Propagating analog signals through a fully digital network on an electronic system prototyping platform,» IEEE International Symposium on Circuits and Systems, ISCAS, 2012.
- Laflamme-Mayer N*, Blaquière Y, Sawan M, « A large range and fine tuning configurable Bandgap reference dedicated to wafer-scale systems,» 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS, 2011.
- Valorge O*, André W*, Savaria Y, Blaquière Y, « Power Supply Analysis of a Large Area Integrated Circuit,» IEEE 9th International New Circuits and Systems Conference, NEWCAS,, 2011.
- Laflamme-Mayer N*, Blaquière Y, Sawan M,, « A Dual-Power Rail, Low-Dropout, Fast-Response Linear Regulator Dedicated to a Wafer-Scale Electronic Systems Prototyping Platform,» IEEE 9th International New Circuits and Systems Conference, NEWCAS,, 2011.
- Badreddine M*, Blaquière Y, Boukadoum M, « Machine-Learning Framework for
Automatic Netlist Creation,» IEEE International Symposium on Circuits and Systems, ISCAS, 2011.
- Bougataya M*, Lakhssassi A, Blaquière Y, Savaria Y, Norman R, Prytula R, « Thermo-Mechanical Analysis of a Reconfigurable Wafer-Scale Integrated
Circuit,» IEEE International Conference on Electronics, Circuits, and Systems, ICECS, 2010.
- Valorge O*, Blaquière Y, Savaria Y, « A Spatially Reconfigurable Fast Differential
Interface for a Wafer Scale Configurable Platform,» IEEE International Conference on Electronics, Circuits, and Systems, ICECS, 2010.
- Diop M D*, Radji M*, Andre W*, Izquierdo R, Blaquière Y, Hamoui A A, « Electrical Characterization of Annular Through Silicon Vias (TSV) for a Reconfigurable Wafer-sized Circuit Board,» IEEE Conference on Electrical Performance of Electronic Packaging and Systems, 2010.
- Laflamme-Mayer N*, Valorge O*, Blaquière Y, Sawan M,, « A Low-Power, Small-Area Voltage Reference Array for a Wafer-Scale Prototyping Platform,» IEEE International New Circuits and Systems Conference, NEWCAS,, 2010.
- Berriah O*, Lakhssassi A, Bougataya M*, Blaquière Y, Savaria Y, « Thermal Analysis of a Miniature Electronic Power Device Matched to a Silicon Wafer,» IEEE International New Circuits and Systems Conference, NEWCAS,, 2010.
- Etienne Lepercq*, Olivier Valorge*, Yan Basile-Bellavance*, Nicolas
Laflamme-Mayer*, Yves Blaquière, Yvon Savaria, An
Interconnection Network for a Novel Reconfigurable Circuit Board,
IEEE MNRC2009 Microsystems and Nanoelectronics Research,
Ottawa, Canada, October 15-16, 2009.
- Yan Basile-Bellavance*, Yves Blaquière,
Yvon Savaria, Faults Diagnosis Methodology for the WaferNet
Interconnection Network, IEEE NEWCAS-TAISA Conference, Toulouse,
France, June 28-July 1st, 2009.
- Etienne Lepercq*, Yves Blaquière, Richard
Norman, Yvon Savaria, Workflow for an
Electronic Configurable Prototyping System, IEEE ISCAS International
Symposium on Circuits and Systems, Taipei, Taiwan, May 24-27, 2009.
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Richard Norman, Olivier Valorge*, Yves Blaquière, Etienne Lepercq*, Yan Basile-Bellavance*, Youssef El-Alaoui*, Richard Prytula, Yvon Savaria, An Active Reconfigurable Circuit Board, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference , Montreal, Canada, June 22-25, pp. 351-354, 2008.
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Richard Norman, Etienne Lepercq*, Yves Blaquière, Olivier Valorge*, Yan Basile-Bellavance*, Richard Prytula and Yvon Savaria, An Interconnection Network for a Novel Reconfigurable Circuit Board, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference , Montreal, Canada, June 22-25, pp. 129-132, 2008.
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Olivier Valorge*, Anh Tuan Nguyen*, Yves Blaquière, Richard Norman and Yvon Savaria, Digital Signal Propagation on a Wafer-Scale Smart Active Programmable Interconnect, IEEE International Conference on Electronics, Circuits and Systems (ICECS'08), Malta, August 31 - September 3, 2008.
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Yan Basile-Bellavance*, Etienne Lepercq*, Yves Blaquière and Yvon Savaria, Hardware/Software System Co-Verification of an Active Reconfigurable Board with SystemC-VHDL, IEEE International Conference on Electronics, Circuits and Systems (ICECS'08) , Malta, Aug 31 - Sep 3, 2008.
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Mohammed Bougataya*, Ahmed Lakhsasi, Richard Norman, Richard Prytula, Yves Blaquière and Yvon Savaria, Steady State Thermal Analysis of a Reconfigurable Wafer-scale Circuit Board, Canadian Conference on Electrical and Computer Engineering (CCECE), Niagara Falls, Canada, May 4-7, pp. 411-416, 2008.
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Yves Blaquière, Yvon Savaria and J. El Fouladi*, Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os, IEEE International conference on Electronics, Circuits and Systems (ICECS'07), Marrakech, Morocco, December, 11-14, 2007.
- Marc-André Cantin*,Yves Blaquière,
Yvon Savaria, Pierre Lavoie, Éric Granger,
Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm
IEEE International Symposium on Circuits and Systems, ISCAS, 2000.
- Marc-André Cantin,
Éric Granger, Yvon Savaria, Yves Blaquière, and Pierre Lavoie.
Four implementation of the fuzzy adaptive resonance theory (ART) neural
network for high data throughput applications.
In Proceedings of the Third International Conference on Cognitive and
Neural Systems, page 15, May 1999.
- Marc-André Cantin,
Yves Blaquière, Éric Granger, Yvon Savaria, and Pierre Lavoie.
Implementation of the fuzzy ART neural network for fast clustering of radar
pulses.
In Proceedings of the IEEE International Symposium on Circuit and
Systems, 1998.
- Pascal Poiré, Yvon
Savaria, Marc-André Cantin, Hervé Daniel, and Yves Blaquière.
A comparative analysis of fuzzy ART neural network implementations: The
advantages of reconfigurable computing.
In Symposium on Field-Programmable Custom Computing Machines
(FCCM'98), 1998.
- Pascal Poiré*, Yvon
Savaria, Hervé Daniel*, Marc-André Cantin*, and Yves Blaquière.
Hardware/software codesign of a fuzzy ART neural clustered: the benefits of configurable computing.
In Proceedings of SPIE International Symposium on Voice, Video, and Data
Communications, volume 3526, November 1998.
- Éric Granger*, Yves
Blaquière, Yvon Savaria, Marc-André Cantin, and Pierre Lavoie.
A VLSI architecture for fast clustering with fuzzy ART neural networks.
International Journal of Microelectronics System Integration,
5(1):3-18, 1997.
- Yves Blaquière, Michel R. Dagenais, and Yvon Savaria.
Timing analysis speed-up using a hierarchical and a multimode approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 15(2):244-255, February 1996.
- Éric Granger*, Yves
Blaquière, Yvon Savaria, Marc-André Cantin*, and Pierre Lavoie.
A VLSI architecture for fast clustering with fuzzy ART neural networks.
Proceedings of the 1996 International Workshop on Neural Networks for
Identification, Control, Robotics, and Signal/Image Processing (NICROSP'96
Workshop), pages 117-125, August 1996.
- Yves
Blaquière, Gabriel Gagné*, Yvon Savaria, and Claude Évéquoz.
A new efficient algorithmic-based SEU tolerant system architecture.
IEEE Transaction on Nuclear Science, 42(6):1599-1606, December
1995.
- Yves
Blaquière, Gabriel Gagné, Yvon Savaria, and Claude Évéquoz.
Cost analysis of a new algorithmic-based soft-error tolerant architecture.
IEEE International Workshop on Defect and Fault Tolerance in VLSI
Systems, pages 189-197, November 1995.
- Yves Blaquière,
Michel R. Dagenais, and Yvon Savaria.
A new accurate and hierarchical timing analysis approach.
In Proceedings of the IEEE European Design Automation Conference,
pages 449-454, 1993.
- Yves Blaquière,
Évaluation rapide des performances temporelles des circuits VLSI: une
approche dynamique et hiérarchique.
PhD thesis, École Polytechnique de Montréal, August 1992.
- Yves Blaquière,
Michel R. Dagenais, and Yvon Savaria.
Fast timing analysis of VLSI circuits: A dynamic and hierarchical approach.
In Proceedings of the IEEE International Symposium on Circuit and
Systems, pages 2399-2402, June 1991.
- Yves
Blaquière and Jacob Davidson.
VHDL design of a priority interrupt controler and synchronizer for mc68008
microprocessor.
In Microprocessor and MicroSystem. Butterworth Scientific Limited,
October 1990.
- Yves
Blaquière and Yvon Savaria.
Area overhead analysis of SEF: a design methodology for tolerating SEU.
IEEE Transactions on Nuclear Science, pages 1481-1486, December
1987.
- Yves Blaquière,
Analyse détaillée du co^ut en matériel apporté par l'approche SEF.
Master's thesis, École Polytechnique de Montréal, August 1986.
- Yves
Blaquière and Yvon Savaria.
Area overhead analysis of soft-errors filtering register.
Conférence canadienne sur le VLSI, pages 26-29, November
1985.
* = Etudiants